Motorola MR 11** TD-R Instrukcja serwisowa - Strona 6

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3.4 Frequency Conditioning

The "Frequency conditioning" module consists of the following circuit parts:

•

Transmitter VCO frequency modulatable via the connection "AFMOD", followed by a non-

selective buffer amplifier for decoupling with an output power at "TXLO" of approx. 10 dBm.

•

Receiver VCO frequency followed by a selective amplifier with an output power for the double

balanced mixer at "RXLO" of approx. 10 dBm.

•

Voltage stabilisation (N151) with additional filtering for the VCOs.

•

Phase locked loop (PLL), consisting of a switchable frequency divider (D361), followed by a

frequency synthesizer (D362) with digital phase comparator (PD), current source output, built-

in voltage inverter for doubling the VCO tuning voltage and controlled by a serial three-wire

bus, a passive, double switchable loop filter, an external PD current adjuster and a reference

oscillator (TCXO, G361).

Function description:

The frequency conditioning takes place according to the principle of frequency analysis in the one

loop (dual modulus) divider method.

The frequency of the free-oscillating transmitter or receiver VCOs (switching through V352, controlled

by port MFO1 of D362 by status word) is divided down to a comparative frequency of 5 or 6.25 kHz

with switchable dividers and compared with an identical high constant comparative frequency

derived from the TCXO frequency of 12.8 MHz in a phase discriminator. This supplies a control

voltage dependent on the frequency and phase deviation which makes sure that the respective

VCO oscillates at the frequency which satisfies the PLL conditions.

To reduce the transient time after frequency change, the loop frequency of the PLL is increased

considerably for a few milliseconds with the positive edge of CSPLL immediately after receiving

the new divider data by external adjustment of the PD current through connection MFO2 of the

frequency synthesizer D362 (effected by V361 and corresponding RC wiring, triggered by line

SCLPLL) and then reduced continuously to such a low value that modulation in the subaudio

range is possible without taking compensatory action. In the meantime, the loop attenuation is

adapted by the resistors R381, 382, 384 in conjunction with the switches V364, 365 in two steps

(same triggering but time constants now by C367, R377, R385).

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