Cypress Semiconductor CY7C1346H Arkusz specyfikacji - Strona 5

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Burst Sequences
The CY7C1346H provides a two-bit wraparound counter, fed
by A
, A
, that implements either an interleaved or linear burst
1
0
sequence. The interleaved burst sequence is designed specif-
ically to support Intel Pentium applications. The linear burst
sequence is designed to support processors that follow a
linear burst sequence. The burst sequence is user selectable
through the MODE input.
Asserting ADV LOW at clock rise will automatically increment
the burst counter to the next address in the burst sequence.
Both Read and Write burst operations are supported.
Sleep Mode
The ZZ input pin is an asynchronous input. Asserting ZZ
places the SRAM in a power conservation "sleep" mode. Two
clock cycles are required to enter into or exit from this "sleep"
mode. While in this mode, data integrity is guaranteed.
Accesses pending when entering the "sleep" mode are not
considered valid nor is the completion of the operation
guaranteed. The device must be deselected prior to entering
the "sleep" mode. CE
, CE
1
2
remain inactive for the duration of t
returns LOW.
ZZ Mode Electrical Characteristics
Parameter
I
Sleep mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ Active to sleep current
ZZI
t
ZZ Inactive to exit sleep current
RZZI
Document #: 38-05672 Rev. *B
, CE
, ADSP, and ADSC must
3
after the ZZ input
ZZREC
Description
Interleaved Burst Address Table
(MODE = Floating or V
First
Second
Address
Address
A
, A
A
, A
1
0
1
0
00
01
01
00
10
11
11
10
Linear Burst Address Table (MODE = GND)
First
Second
Address
Address
A
, A
A
, A
1
0
1
0
00
01
01
10
10
11
11
00
Test Conditions
ZZ > V
– 0.2V
DD
ZZ > V
– 0.2V
DD
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
CY7C1346H
)
DD
Third
Fourth
Address
Address
A
, A
A
, A
1
0
1
0
10
11
11
10
00
01
01
00
Third
Fourth
Address
Address
A
, A
A
, A
1
0
1
0
10
11
11
00
00
01
01
10
Min.
Max.
Unit
40
mA
2t
ns
CYC
2t
ns
CYC
2t
ns
CYC
0
ns
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