Cypress Semiconductor CY7C1346H Arkusz specyfikacji - Strona 6

Przeglądaj online lub pobierz pdf Arkusz specyfikacji dla Sprzęt komputerowy Cypress Semiconductor CY7C1346H. Cypress Semiconductor CY7C1346H 16 stron. 2-mbit (64k x 36) pipelined sync sram

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[2, 3, 4, 5, 6, 7]
Truth Table
Next Cycle
Add. Used
Deselect Cycle,
None
Power-down
Deselect Cycle,
None
Power-down
Deselect Cycle,
None
Power-down
Deselect Cycle,
None
Power-down
Deselect Cycle,
None
Power-down
Sleep Mode,
None
Power-down
READ Cycle,
External
Begin Burst
READ Cycle,
External
Begin Burst
WRITE Cycle,
External
Begin Burst
READ Cycle,
External
Begin Burst
READ Cycle,
External
Begin Burst
READ Cycle,
Next
Continue Burst
READ Cycle,
Next
Continue Burst
READ Cycle,
Next
Continue Burst
READ Cycle,
Next
Continue Burst
WRITE Cycle,
Next
Continue Burst
WRITE Cycle,
Next
Continue Burst
READ Cycle,
Current
Suspend Burst
READ Cycle,
Current
Suspend Burst
READ Cycle,
Current
Suspend Burst
READ Cycle,
Current
Suspend Burst
Notes:
2. X = "Don't Care." H = Logic HIGH, L = Logic LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
(BW
,BW
,BW
,BW
), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
, CE
, and CE
are available only in the TQFP package.
1
2
3
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are Tri-State when OE
is inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05672 Rev. *B
CE
CE
CE
ZZ
ADSP
1
2
3
H
X
X
L
L
L
X
L
L
X
H
L
L
L
X
L
L
X
H
L
X
X
X
H
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
L
H
L
L
X
X
X
L
X
X
X
L
H
X
X
L
H
X
X
L
X
X
X
L
H
X
X
L
X
X
X
L
X
X
X
L
H
X
X
L
H
X
X
L
,BW
,BW
A
B
C
ADSC
ADV
WRITE
X
L
X
L
X
X
L
X
X
H
L
X
H
L
X
X
X
X
L
X
X
L
X
X
H
L
X
H
L
X
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
H
H
L
X
H
L
H
H
H
H
H
H
X
H
H
X
H
H
,BW
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
D
. Writes may occur only on subsequent clocks
[A:D]
CY7C1346H
OE
CLK
DQ
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
L-H
Tri-State
X
X
X
Tri-State
X
L
L-H
Q
X
H
L-H
Tri-State
L
X
L-H
D
H
L
L-H
Q
H
H
L-H
Tri-State
H
L
L-H
Q
H
H
L-H
Tri-State
H
L
L-H
Q
H
H
L-H
Tri-State
L
X
L-H
D
L
X
L-H
D
H
L
L-H
Q
H
H
L-H
Tri-State
H
L
L-H
Q
H
H
L-H
Tri-State
Page 6 of 16
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