DG UDP10G-IP Manual de configuração - Página 8
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4) Turn on power switch on FPGA board.
5) For Arria10 SoC board, set programmable clock to 322.265625 MHz by using "Clock
Control" application as following step.
a. Open "Clock Controller" application.
b. Select Si5338 tab (U50) and set CLK3 frequency = 322.265625 MHz.
c. Click "Set" button and wait until the application is active again.
d. Close Clock controller application.
26-Aug-20
Figure 1-7 Reference clock programming
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