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Symbol
Space between differential pair signals (CLK+
S
DP
[5]
DIF–
)
Space between differential signals and GND, between differential CLK± and
S
DD
differential DIF±, or between differential DIF± and other differential DIF±
S
Space between differential signals and logic signals
DC
W
Width of trace
PCB
Length difference between the true (+) and complement (–) signals of a
L
DP
differential pair (CLK+ and CLK–, or DIF+ and DIF–)
Length difference between any two differential signals (CLK± and DIF±, or
L
DD
between DIF± and any other DIF±)
3
PCB Design Considerations
3.1
Layer Layout
Balanced transmission lines for the FPD-Link signals may be implemented as any of the following types:
▪
Edge-coupled microstrip
▪
Edge-coupled stripline
▪
Broadside-coupled stripline
This application note shows edge-coupled microstrip in the examples.
If the PCB has four or more layers, use the structure shown in
on one side of the board, and the noisy logic traces on the opposite side of the board.
2
CLK+ is the true/positive (+) signal of the differential clock
3
CLK– is the complement/negative (–) signal of the differential clock
4
DIF+ is the true/positive (+) signal of a differential data line
5
DIF– is the complement/negative (–) signal of a differential data line
6
This value is determined by the specifications of the layer thicknesses and dielectric materials used by the board manufacturer.
To ensure proper differential impedance in manufacturing, it is recommended to include a test transmission line on a coupon
adjacent to each board, and verify the transmission line impedance as part of the test process of the bare board.
7
For microstrip transmission lines in FR-4 with a dielectric constant of 4.7
8
While any of these transmission line constructs can be used, they should not be mixed; i.e., do not use balanced microstrip for
some of the signals and balanced stripline for others. The signals propagate at different rates on these transmission lines, which
makes it difficult to maintain matched delays.
9
Most design equations for microstrip and balanced microstrip do not take into account the dielectric impact of the soldermask layer.
When selecting a new board manufacturer, a test board allowing evaluation of multiple different spacings is recommended to
determine the target values for the board design.
10
Do not use gold-plated traces as a replacement for soldermask. The nickel diffusion-barrier layer has ferromagnetic properties
that distort high-speed signals.
11
LVDS signals are ground-referenced. When implementing balanced microstrip transmission lines, it is preferred to have them
coupled to a ground plane instead of a power plane. When coupled to a power plane, noise on that supply is coupled as common-
mode noise to the signals on the transmission lines.
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FPD-Link PCB Guidelines for the Traveo Family S6J3200 Series MCUs
Table 1. PCB Layout Trace Space, Width, and Length
Description
[2]
[3]
and CLK–
[7]
[7]
[9, 10]
Document No. 002-11139 Rev. *A
Recommended
Dimensions
[4]
or DIF+
and
Minimum Pair
[6]
spacing
Minimum Pair
spacing x 2
Minimum Pair
spacing x 4
Trace width
Maximum 5 mm
Maximum 5 mm
Figure
1. This places the balanced microstrip traces
As shown in
Figure 1, Figure 2, Figure 3
Figure 1, Figure 2, Figure 3
Figure 2
[6]
Figure 1, Figure 2, Figure 3
Figure 4
Figure 4
[8]
[11]
2