Cypress Semiconductor CY7C1218H Ficha de especificações - Página 4

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Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. All data outputs pass through

output registers controlled by the rising edge of the clock.

The CY7C1218H supports secondary cache in systems

utilizing either a linear or interleaved burst sequence. The

interleaved burst order supports Pentium and i486™

processors. The linear burst sequence is suited for processors

that utilize a linear burst sequence. The burst order is user

selectable, and is determined by sampling the MODE input.

Accesses can be initiated with either the Processor Address

Strobe (ADSP) or the Controller Address Strobe (ADSC).

Address advancement through the burst sequence is

controlled by the ADV input. A two-bit on-chip wraparound

burst counter captures the first address in a burst sequence

and automatically increments the address for the rest of the

burst access.

Byte Write operations are qualified with the Byte Write Enable

(BWE) and Byte Write Select (BW

Enable (GW) overrides all Byte Write inputs and writes data to

all four bytes. All Writes are simplified with on-chip

synchronous self-timed Write circuitry.

Three synchronous Chip Selects (CE

asynchronous Output Enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE

is HIGH.

Single Read Accesses

This access is initiated when the following conditions are

satisfied at clock rise: (1) ADSP or ADSC is asserted LOW,

(2) CE

, CE

are all asserted active, and (3) the Write

signals (GW, BWE) are all deasserted HIGH. ADSP is ignored

if CE

is HIGH. The address presented to the address inputs

(A) is stored into the address advancement logic and the

address register while being presented to the memory array.

The corresponding data is allowed to propagate to the input of

the output registers. At the rising edge of the next clock the

data is allowed to propagate through the output register and

onto the data bus within t

exception occurs when the SRAM is emerging from a

deselected state to a selected state, its outputs are always

tri-stated during the first cycle of the access. After the first cycle

of the access, the outputs are controlled by the OE signal.

Consecutive single Read cycles are supported. Once the

SRAM is deselected at clock rise by the chip select and either

ADSP or ADSC signals, its output will tri-state immediately.

Single Write Accesses Initiated by ADSP

This access is initiated when both of the following conditions

are satisfied at clock rise: (1) ADSP is asserted LOW, and

(2) CE

, CE

are all asserted active. The address

presented to A is loaded into the address register and the

address advancement logic while being delivered to the

memory array. The Write signals (GW, BWE, and BW

ADV inputs are ignored during this first cycle.

ADSP-triggered Write accesses require two clock cycles to

complete. If GW is asserted LOW on the second clock rise, the

data presented to the DQ inputs is written into the corre-

sponding address location in the memory array. If GW is HIGH,

then the Write operation is controlled by BWE and BW

Document #: 38-05667 Rev. *B

) inputs. A Global Write

[A:D]

, CE

) and an

if OE is active LOW. The only

) and

[A:D]

signals. The CY7C1218H provides Byte Write capability that

is described in the Write Cycle Descriptions table. Asserting

the Byte Write Enable input (BWE) with the selected Byte

Write (BW

) input, will selectively write to only the desired

[A:D]

bytes. Bytes not selected during a Byte Write operation will

remain unaltered. A synchronous self-timed Write mechanism

has been provided to simplify the Write operations.

Because the CY7C1218H is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQ are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Single Write Accesses Initiated by ADSC

ADSC Write accesses are initiated when the following condi-

tions are satisfied: (1) ADSC is asserted LOW, (2) ADSP is

deasserted HIGH, (3) CE

and (4) the appropriate combination of the Write inputs (GW,

BWE, and BW

) are asserted active to conduct a Write to

[A:D]

the desired byte(s). ADSC-triggered Write accesses require a

single clock cycle to complete. The address presented to A is

loaded

into

the

address

advancement logic while being delivered to the memory array.

The ADV input is ignored during this cycle. If a global Write is

conducted, the data presented to DQs is written into the corre-

sponding address location in the memory core. If a Byte Write

is conducted, only the selected bytes are written. Bytes not

selected during a Byte Write operation will remain unaltered.

A synchronous self-timed Write mechanism has been

provided to simplify the Write operations.

Because the CY7C1218H is a common I/O device, the Output

Enable (OE) must be deasserted HIGH before presenting data

to the DQ inputs. Doing so will tri-state the output drivers. As

a safety precaution, DQs are automatically tri-stated whenever

a Write cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1218H provides a two-bit wraparound counter, fed

by A

, A

, that implements either an interleaved or linear burst

sequence. The interleaved burst sequence is designed specif-

ically to support Intel Pentium applications. The linear burst

sequence is designed to support processors that follow a

linear burst sequence. The burst sequence is user selectable

through the MODE input.

Asserting ADV LOW at clock rise will automatically increment

the burst counter to the next address in the burst sequence.

Both Read and Write burst operations are supported.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation "sleep" mode. Two

clock cycles are required to enter into or exit from this "sleep"

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the "sleep" mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the "sleep" mode. CE

, CE

remain inactive for the duration of t

returns LOW.

CY7C1218H

, CE

are all asserted active,

and

the

address

, CE

, ADSP, and ADSC must

after the ZZ input

ZZREC

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