Cypress Semiconductor CY7C1218H Ficha de especificações - Página 5

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Interleaved Burst Address Table
(MODE = Floating or V
First
Second
Address
Address
A
, A
A
, A
1
0
1
0
00
01
01
00
10
11
11
10
ZZ Mode Electrical Characteristics
Parameter
I
Sleep mode standby current
DDZZ
t
Device operation to ZZ
ZZS
t
ZZ recovery time
ZZREC
t
ZZ Active to sleep current
ZZI
t
ZZ Inactive to exit sleep current
RZZI
[2, 3, 4, 5, 6, 7]
Truth Table
Next Cycle
Add. Used
Unselected
None
Unselected
None
Unselected
None
Unselected
None
Unselected
None
Begin Read
External
Begin Read
External
Continue Read
Next
Continue Read
Next
Continue Read
Next
Continue Read
Next
Suspend Read
Current
Suspend Read
Current
Suspend Read
Current
Suspend Read
Current
Begin Write
Current
Begin Write
Current
Begin Write
External
Notes:
2. X = "Don't Care." H = HIGH, L = LOW.
3. WRITE = L when any one or more Byte Write Enable signals (BW
(BW
,BW
,BW
,BW
), BWE, GW = H.
A
B
C
D
4. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.
5. CE
, CE
, and CE
are available only in the TQFP package.
1
2
3
6. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BW
after the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the Write cycle to allow the outputs to Tri-State. OE is a
don't care for the remainder of the Write cycle.
7. OE is asynchronous and is not sampled with the clock rise. It is masked internally during Write cycles. During a Read cycle all data bits are tri-state when OE is
inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).
Document #: 38-05667 Rev. *B
)
DD
Third
Fourth
Address
Address
A
, A
A
, A
1
0
1
0
10
11
11
10
00
01
01
00
Description
ZZ
CE
CE
CE
1
2
L
H
X
X
L
L
X
H
L
L
L
X
L
L
X
H
L
L
L
X
L
L
H
L
L
L
H
L
L
X
X
X
L
X
X
X
L
H
X
X
L
H
X
X
L
X
X
X
L
X
X
X
L
H
X
X
L
H
X
X
L
X
X
X
L
H
X
X
L
L
H
L
,BW
A
Linear Burst Address Table (MODE = GND)
First
Second
Address
Address
A
, A
A
1
0
1
00
01
01
10
10
11
11
00
Test Conditions
ZZ > V
– 0.2V
DD
ZZ > V
– 0.2V
DD
ZZ < 0.2V
This parameter is sampled
This parameter is sampled
ADSP
ADSC
ADV
3
X
L
X
L
X
X
L
X
X
H
L
X
H
L
X
L
X
X
H
L
X
H
H
L
H
H
L
X
H
L
X
H
L
H
H
H
H
H
H
X
H
H
X
H
H
H
H
H
X
H
H
H
H
X
,BW
,BW
) and BWE = L or GW = L. WRITE = H when all Byte Write Enable signals
B
C
D
[A:D]
CY7C1218H
Third
Fourth
Address
Address
, A
A
, A
A
0
1
0
10
11
00
01
Min.
Max.
40
2t
CYC
2t
CYC
2t
CYC
0
OE
DQ
X
Tri-State
X
Tri-State
X
Tri-State
X
Tri-State
X
Tri-State
X
Tri-State
X
Tri-State
H
Tri-State
L
DQ
H
Tri-State
L
DQ
H
Tri-State
L
DQ
H
Tri-State
L
DQ
X
Tri-State
X
Tri-State
X
Tri-State
. Writes may occur only on subsequent clocks
Page 5 of 16
, A
1
0
11
00
01
10
Unit
mA
ns
ns
ns
ns
Write
X
X
X
X
X
X
Read
Read
Read
Read
Read
Read
Read
Read
Read
Write
Write
Write
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