DTK PIM-TB10 Руководство пользователя - Страница 6
Просмотреть онлайн или скачать pdf Руководство пользователя для Материнская плата DTK PIM-TB10. DTK PIM-TB10 14 страниц.
Печатать страницу
A channel check line exists for reoorting error conditions to
the processor Activating this line results in a Non-Maskable In
terrupt (NMil to the 8088 processor. Memory expansion options
use this line to report parity errors.
The I/O channel is repowered, to provide sufficient drive, to
power all eight (J1 through J8)
expansion~lots.
assuming two
Low-Power Schorttky (LS) loads per slot. The I/O adapters
typically use only one load.
1,3
1/0
Channel Description
The following is a description of the PC/XT I/O Channel.
All lines are TTL-compatible.
Singal I/O
Description
OSC, Oscillator:
High: speed clock with a 70-ns period (14.31818 MHz).
It has a 50% duty cycle.
CLK, System Clock:
It is divide-by-three of the oscil'lator and has a period of
210 ns (4.77 MHz). The clock has a 33% duty cycle.
RESET:
This line is used to reset or initialize- system logic upon
power-up or during a low line voltage outage.
This signal is
synchronized to the falling edge of clock and is active high.
AO-A 19, Address
Bits 0
to 19:
These lines are used to address memory.and I/O devices with
in the system. The 20 address lines allow access of up to 1 meg
abyte of memory. AO is the Least Significant Bit (LSB) and A 19
is the Most Significant Bit (MSBI. These lines are generated by
either the processor or OMA controller. They
ar~
active high.
00-07,
I/O
Data
Bits 0
to
7:
These lines provide data bus bits 0 to 7 for the processor.
7
6.