DTK PIM-TB10 Руководство пользователя - Страница 5

Просмотреть онлайн или скачать pdf Руководство пользователя для Материнская плата DTK PIM-TB10. DTK PIM-TB10 14 страниц.

Печатать страницу

- MEMORY-

The system board supports both ROM/EPROM and RIW

memory. it has space for 32k x 1 & 8k x 1 of ROM or EPROM:

this ROM contains the power-on self-test, I/O drivers, dot patterns

for 128 characters in gr.aphics mode, and a diskette.

The system board also has from 256k to 640k' of RIW

memory. A minimum system would have 256k of memory.

- KEYBOARD-

The system board contains the adapter circuits for attaching

the serial interface from the keyboard. These circuits generate an

interrupt on to the processor, when a complete scan code is

received. The interface can request execution of a diagnostic test

in the keyboard.

The keyboard interface is a 5'pin DIN connector on th.e

system board, that extends through the rear panel of the system

unit.

-SPEAKER

The system units has an 2'f.. inch audio speaker. The speaker's

control circuits and driver are on the system board. The speaker

connects through a 2-wire interface that attaches to a 3-pin

connector on the system board.

The speaker drive circuit could be capable of providing

approximately

' 1 2

watt of power.

The control circuits allow the

speaker to be driven three different ways: 1) a direct program

control register bit may be toggled, to generate a pulse train; 2)

the output from Channel 2 of the timer coun ter, may be prog

ramed to generate a wavefrom to the speaker; 3) the clock input

to the timer counter, can be modulated with a program controlled

I/O register bit.

All three methods may be performed simul

taneously.

1-2 Expansion I/O Channel

The I/O channel is an extension of the 8088 microprocessor

bus.

It is, however, demultiplexed, repowered, and enhanced by

the addition of interrupts and Direct Memory Access (DMA)

functions.

The I/O channel contains'an 8 bit, bidirectional data bus, 20

address lines, 6 levels of interrupt, control lines for memory and

I/O read or write, clock and timing lines,'3

chann~'s

of DMA

control lines, memory refresh timing control lines, a channel check

line, and power and ground for the adapters. Four voltage levels

~re

provided for I/O.card: +5Vdc, -5Vdc, +12 Vdc, and -12dc.

These functions are provided in a 62-pin connector with lOa-mil

card tab sp'acing.

A "ready" lines is available on the I/O channel, to allow

operation with slow I/O or memory' devices. If the channel's ready

line is not activated by an addressed device, all processor-generated

memory read and write cycles takes four 210-ns clock or 840

ns/byte. All processor-generated I/O read and write .cycles require

five clocks for a cycle time of 1.05J.(s/byte. Refresh cycles occur

once every 72 clocks (approximatefy 15

p.s)

and require four

clocks or approximately 7% ofthe bus bandwidth.

I/O devices are addressed using I/O mapped address space.

The channel is designed so that 768 I/O device addressed are

available to the

1/0

channel cards.