Cypress Semiconductor Rambus XDR CY24271 Технический паспорт - Страница 3
Просмотреть онлайн или скачать pdf Технический паспорт для Компьютерное оборудование Cypress Semiconductor Rambus XDR CY24271. Cypress Semiconductor Rambus XDR CY24271 13 страниц. Clock generator with zero sda hold time
Печатать страницу
PLL Multiplier
Table 3
shows the frequency multipliers in the PLL, selectable by programming the SMBus registers MULT0, MULT1, and MULT2.
Default multiplier at power up is 4.
Table 3. PLL Multiplier Selection
Register
MULT2
MULT1
MULT0
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Input Clock Signal
The XCG receives either a differential (REFCLK/REFCLKB) or a
single-ended reference clocking input (REFCLK).
When the reference input clock is from a different clock source,
it must meet the voltage levels and timing requirements listed in
DC Operating Conditions
on page 7 and
tions
on page 8.
For a single-ended clock input, an external voltage divider and a
supply voltage, as shown in
reference voltage V
at the REFCLKB pin. This determines the
TH
proper trip point of REFCLK. For the range of V
DC Operating Conditions
on page 7, the outputs also meet the
DC and AC Operating Conditions tables.
Table 4. SMBus Device Addresses for CY24272
XCG
Device
Operation
Write
0
Read
Write
1
Read
Write
2
Read
Write
3
Read
Notes
1. Output frequencies shown in
Table 3
modulated input clock with maximum and minimum input cycle time. The REFSEL bit in SMBus 81h is set correctly as shown.
2. Default PLL multiplier at power up.
Document Number: 001-42414 Rev. **
Frequency Multiplier
REFCLK = 100 MHz
3
4
5
6
Reserved
9/2
Reserved
15/4
AC Operating Condi-
Figure 2
on page 6, provide a
specified in
TH
Hex
Address
Five Most Significant Bits
D8
D9
DA
DB
1
1
DC
DD
DE
DF
are based on nominal input frequencies of 100 MHz and 133.3 MHz. The PLL multipliers are applicable to spread spectrum
Output Frequency (MHz)
[1]
, REFSEL = 0 REFCLK = 133 MHz
300
[2]
400
500
600
–
450
–
375
Modes of Operation
The modes of operation are determined by the logic signals
applied to the EN and /BYPASS pins and the values in the five
SMBus Registers: RegTest, RegA, RegB, RegC, and RegD.
Table 5
on page 4 shows selection from one to all four of the
outputs, the Outputs Disabled Mode (EN = low), and Bypass
Mode (EN = high, /BYPASS = low). There is an option reserved
for vendor test. Disabled outputs are set to High Z.
At power up, the SMBus registers default to the last entry in
6
on page 5. The value at RegTest is 0. The values at RegA,
RegB, RegC, and RegD are all '1'. Thus, all outputs are
controlled by the logic applied to EN and /BYPASS.
8-bit SMBus Device Address Including Operation
ID1
0
0
0
1
1
1
1
CY24272
[1]
, REFSEL = 1
400
–
667
–
–
600
–
500
ID0
WR# / RD
0
0
1
0
1
1
0
0
1
0
1
1
Page 3 of 13
Table
[+] Feedback