Cypress Semiconductor CY7C1006D Şartname Sayfası - Sayfa 5

Bilgisayar Donanımı Cypress Semiconductor CY7C1006D için çevrimiçi göz atın veya pdf Şartname Sayfası indirin. Cypress Semiconductor CY7C1006D 12 sayfaları. 1-mbit (256k x 4) static ram

Sayfayı Yazdır
Switching Characteristics
Parameter
Read Cycle
[7]
t
V
(typical) to the first access
power
CC
t
Read Cycle Time
RC
t
Address to Data Valid
AA
t
Data Hold from Address Change
OHA
t
CE LOW to Data Valid
ACE
t
OE LOW to Data Valid
DOE
t
OE LOW to Low Z
LZOE
t
OE HIGH to High Z
HZOE
t
CE LOW to Low Z
LZCE
t
CE HIGH to High Z
HZCE
[10]
t
CE LOW to Power-Up
PU
[10]
t
CE HIGH to Power-Down
PD
[11, 12]
Write Cycle
t
Write Cycle Time
WC
t
CE LOW to Write End
SCE
t
Address Set-Up to Write End
AW
t
Address Hold from Write End
HA
t
Address Set-Up to Write Start
SA
t
WE Pulse Width
PWE
t
Data Set-Up to Write End
SD
t
Data Hold from Write End
HD
t
WE HIGH to Low Z
LZWE
t
WE LOW to High Z
HZWE
Notes
6. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified
I
/I
and 30-pF load capacitance.
OL
OH
7. t
gives the minimum amount of time that the power supply should be at typical V
POWER
8. t
, t
, and t
are specified with a load capacitance of 5 pF as in part (c) of
HZOE
HZCE
HZWE
enter a high impedance state.
9. At any given temperature and voltage condition, t
10. This parameter is guaranteed by design and is not tested.
11. The internal write time of the memory is defined by the overlap of CE and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of these signals
can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
Document #: 38-05459 Rev. *E
[6]
(Over the Operating Range)
Description
[8, 9]
[9]
[8, 9]
[9]
[8, 9]
"AC Test Loads and Waveforms
is less than t
, t
is less than t
HZCE
LZCE
HZOE
7C106D-10
7C1006D-10
Min
Max
100
10
10
3
10
0
3
0
10
7
7
0
0
7
6
0
3
values until the first memory access can be performed.
CC
[5]
" on page
4. Transition is measured when the outputs
, and t
is less than t
for any given device.
LZOE
HZWE
LZWE
CY7C106D
CY7C1006D
Unit
µs
ns
ns
ns
ns
5
ns
ns
5
ns
ns
5
ns
ns
10
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
5
ns
Page 5 of 11
[+] Feedback