Alpha Data ADM-SDEV-CFG1 Посібник користувача - Сторінка 10
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Друкувати сторінку3.3 Clocks
The ADM-SDEV-CFG1 board can provide two different clock sources to the Base board FPGA.
One clock source is generated by an on board oscillator and the other can be input via connector J4.
Source
External (J5)
Oscillator
The ADM-SDEV-CFG1 board can also output a clock signal via connector J4.
This clock is generated by the FPGA on the base board.
Source
FPGA
3.4 IPASS Connector
One of the high speed serial lanes is connected to an IPASS connector for remote PCIe connection.
Connector
IPASS (J6)
3.5 SATA Connectors
The ADM-SDEV-CFG1 board has two standard right angle SATA receptacles for use with SATA compliant
storage devices.
Connector
SATA_1 (J7)
SATA_2 (J8)
3.6 Health Monitoring
The ADM-SDEV-BASE has the ability to monitor temperature and voltage to maintain a check on the operation
of the board. The monitoring is implemented using the Atmel AVR microcontroller.
The system monitor microcontroller can be accessed via the USB connector (J3), please refer to the
Page 6
Signal
Frequency
CLK2_M2C_0
Variable
CLK2_M2C_1
150MHz Fixed
Table 3 : Input CLK_M2C Connections
Signal
Frequency
DP1_C2M_1
Variable
Table 4 : Output Clock Connection
Signal
DP0_C2M
DP0_M2C
GBTCLK0_M2C
Table 5 : IPASS PCIe Connections
Signal
DP2_C2M
DP2_M2C
DP3_C2M
DP3_M2C
Table 6 : SATA Connections
FPGA Input
Bank 24
Bank 24
FPGA Input
MGT Quad 224
FPGA Bank
MGT Quad 224
MGT Quad 224
MGT Quad 224
FPGA Bank
MGT Quad 224
MGT Quad 224
MGT Quad 224
MGT Quad 224
ADM-SDEV-CFG1 User Manual
V1.2 - 18th March 2020
IO
"P" pin
Standard
LVDS
AM32
LVDS
AM31
IO
"P" pin
Standard
LVDS
AV6
"P" pin
"N" pin
AW8
AW7
AW4
AW3
AT10
AT9
"P" pin
"N" pin
AU8
AU7
AU4
AU3
A16
A15
A12
A11
Functional Description
ad-ug-1361_v1_2.pdf
"N" pin
AN32
AN31
"N" pin
AV5