Alpha Data ADM-SDEV-CFG1 Посібник користувача - Сторінка 9
Переглянути онлайн або завантажити pdf Посібник користувача для Комп'ютерне обладнання Alpha Data ADM-SDEV-CFG1. Alpha Data ADM-SDEV-CFG1 12 сторінок.
Друкувати сторінкуADM-SDEV-CFG1 User Manual
V1.2 - 18th March 2020
Comp. Ref.
D1(Green)
3.2 JTAG Interface
3.2.1 On-board Interface
The JTAG boundary scan chain can be accessed via a standard header (J2).
This allows the connection of the Xilinx JTAG cable for FPGA debug and QSPI Flash programming via the Xilinx
toolchain.
The JTAG chain starts on the config FMC board and through the Base board, passing through the FPGA, the
LPC FMC (if fitted) and the FMC+ (if fitted).
The scan chain is shown in
FMC2_TDI
Config
FMC
(J2)
FMC2_TDO
3.2.2 JTAG Voltages
The Vcc supply provided to the JTAG cable on the config header is +3.3V and is protected by a poly fuse rated at
375mA.
The voltage level of the JTAG chain on the ADM-SDEV-BASE board is set to the config FMC adjustable voltage
FMC2_VIO.
Functional Description
ad-ug-1361_v1_2.pdf
Function
ON State
3.3V Supply
Normal operation
Status
JTAG Boundary Scan
FPGA_TDI
Level Shift
3V3 -> FMC2_VIO
HDR_TDO
Figure 4 : JTAG Boundary Scan Chain
Table 2 : LED Definitions
Chain:
FPGA
FPGA_TDO
XCKU060
Off State
Power Off
FMC1_TDI
Level Shift
FMC2_VIO –> 3V3
FMC1_TDO
En#
FMC1_PRESENT#
FMC3_TDI
Level Shift
FMC2_VIO –> 3V3
FMC3_TDO
En#
FMC3_PRESENT#
LPC
FMC
(J1)
FMC+
(J3)
Page 5