EG&G ORTEC 553 Посібник з експлуатації та обслуговування - Сторінка 11
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Друкувати сторінкуfurnished as a dc level through CN3 on the rear panel.
Switch 84 on the rear panel selects which of these
sources is effective for bias control.
For the internal bias circuit, R47 is a potentiometer
mounted on the printed circuit that adjusts the minimum
level for the front panel control. The actual range of R43
is, then, from a few millivolts to about —5 V. The adjusted
level is buffered through IC2(7) and inverted through
operational amplifier IC2{1), with a gain of unity, and
furnished to the inverting input of IC4, the lower level
discriminator.
For the external bias circuit, a dc level between 0 and
-10 V can be furnished through CN3 and divided by R44
and R45. The result that is selected with switch 84 is
then furnished through the same buffering and coupling
network to the lower level discriminator.
5.4.
UPPER LEVEL BIAS
The threshold for the upper level discriminator is ad
justed with the front panel Window or Upper Level
control, R38. The range for this control is 0 to -5 V. The
adjusted level is buffered through IC1(7) and furnished
through either R55 or R52, through operational amplifier
IC1(1), and to the inverting input of upper level discrimi
nator IC3. When switch 81 is set at either Integrate or
Normal, the gain of IC1{1) for this adjusted bias signal is
1.0; when the switch selects Window, the gain is reduced
to 0.1 and the effective range of the Window control is
thus reduced by a factor of 10. Also, when the switch
selects Window, the level that is furnished from IC2(7)
for the lower level discriminator is also furnished through
R50 and IC1(1). Thus the adjusted lower level becomes,
effectively, the base above which the upper level is added,
and the result is a window of 0 to 1 V between the lower
level and upper level thresholds (referred to the input
pulse amplitude). The gain for the level from IC2(7)
through IC1(1) is unity.
5.5. INPUT CIRCUIT
The analog input signal is furnished through CN2 on the
front panel. The signal is then furnished to dividers R3-
R4 and R147-R148, and 50% of the input amplitude is
applied to the noninverting inputs of both the UL and LL
discriminators, IC3 and 104. The input range of 0 to
+10 V, divided by two for an effective range of 0 to +5 V
at the discriminator inputs, is directly equivalent to the
range of threshold levels described in 8ections 5.2 and
5.3.
The input signal, through the front panel dc-coupled
circuit, can be monitored at test point TP1 on the front
panel.
5.6. LOWER LEVEL DISCRIMINATOR
Integrated circuit package 104 is the lower level discrimi
nator. As long as the input level at its pin 3 does not
exceed the level at pin 4, the output at its pin 9 is high.
When the amplitude of the input signal, at pin 3, in
creases above the threshold level at pin 4, 104 triggers
and reverses the levels at its pins 9 and 11. When 104(11)
goes high, 106(13) goes low and latches 104(11) in the
high state until a reset is furnished from 107(6). The reset
will be furnished when the discriminator returns to quies
cent and the OF discriminator is also reset; these condi
tions occur on the trailing edge of the input pulse.
Until latch 106(13) and 104(11) is reset, the high level to
pin 2 of 80A gate 107(12) arms the gate to permit
response if its pins 1 and 13 go high. 8ee 8ection 5.9,
80A Gate.
5.7. UPPER LEVEL DISCRIMINATOR
Integrated circuit package 103 is the upper level discrim
inator. It is identical to 104, discussed in 8ection 5.6,
except that its output at pin 9 is not used.
If the amplitude at pin 3 increases above the threshold
level at pin 4, 103 triggers and switches the output at
103(11) to its high state. This output at pin 11 latches
through 106(10) until a reset is furnished from 107(6).
The reset will be furnished when both the lower level and
OF discriminators have been reset, as discussed in
8ection 5.6.
At the trigger time on the leading edge of the input
signal, when 103(11) goes high, an output through 0N4,
the UL Out connector, is generated through 108(1), 022,
023, and 024. The positive output pulse has a width of
about 500 ns.
If switch 81 is set at Int, the output of gate 107(8) will
remain high whether the upper level discriminator is
triggered or not. But if the switch selects either Normal
or Window (for differential single-channel operation), a
response in 103 will furnish a low signal from 107(8) to
inhibit a response in 107(12) and prevent an 80A output
signal from being generated.
5.8. CONSTANT FRACTION CIRCUIT
The input signal is furnished through R2 into a peak
detect circuit, formed by Q1 through Q5 and O10. During
the rise time of the input pulse, the capacitor is charged.
The reverse current path is cut off, so the peak amplitude
of the input pulse remains on O10 until it is discharged at
a later time.
The peak amplitude of the input pulse is furnished
through a unity-gain buffer amplifier, Q8, Q9, and Q10.
The front panel Walk Adj control, R36, provides a fine
adjustment of the offset of this amplifier and is adjusted
for its dynamic function to minimize walk in the time-
significant output pulses. The output of the buffer ampli
fier is furnished through R33 and R31, a divide-by-4
attenuator. From this circuit, 25% of the peak amplitude
of the signal input pulse is furnished to the inverting
input of 105.