Cypress Semiconductor NoBL CY7C1352G 사양 시트
{카테고리_이름} Cypress Semiconductor NoBL CY7C1352G에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor NoBL CY7C1352G 13 페이지. 4-mbit (256k x 18) pipelined sram with nobl architecture
페이지 인쇄Features
• Pin compatible and functionally equivalent to ZBT™
devices
• Internally self-timed output buffer control to eliminate
the need to use OE
• Byte Write capability
• 256K x 18 common I/O architecture
• 3.3V core power supply (V
• 2.5V/3.3V I/O power supply (V
• Fast clock-to-output times
— 2.6 ns (for 250-MHz device)
• Clock Enable (CEN) pin to suspend operation
• Synchronous self-timed writes
• Asynchronous output enable (OE)
• Available in lead-free 100-Pin TQFP package
• Burst Capability—linear or interleaved burst order
• ZZ" Sleep Mode Option and Stop Clock option
Logic Block Diagram
A0, A1, A
MODE
CLK
C
CEN
ADV/LD
BW
A
BW
B
WE
OE
CE1
CE2
CE3
ZZ
Note:
1. For best-practices recommendations, please refer to the Cypress application note System Design Guidelines on www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05514 Rev. *D
4-Mbit (256K x 18) Pipelined SRAM with
)
DD
)
DDQ
ADDRESS
REGISTER 0
A1
D1
A0
BURST
D0
LOGIC
ADV/LD
C
WRITE ADDRESS
WRITE ADDRESS
REGISTER 1
REGISTER 2
WRITE REGISTRY
AND DATA COHERENCY
CONTROL LOGIC
READ LOGIC
Sleep
Control
•
198 Champion Court
NoBL™ Architecture
Functional Description
The CY7C1352G is a 3.3V, 256K x 18 synchronous-pipelined
Burst SRAM designed specifically to support unlimited true
back-to-back Read/Write operations without the insertion of
wait states. The CY7C1352G is equipped with the advanced
No Bus Latency™ (NoBL™) logic required to enable consec-
utive Read/Write operations with data being transferred on
every clock cycle. This feature dramatically improves the
throughput of the SRAM, especially in systems that require
frequent Write/Read transitions.
All synchronous inputs pass through input registers controlled
by the rising edge of the clock. All data outputs pass through
output registers controlled by the rising edge of the clock. The
clock input is qualified by the Clock Enable (CEN) signal,
which, when deasserted, suspends operation and extends the
previous clock cycle. Maximum access delay from the clock
rise is 2.6 ns (250-MHz device).
Write operations are controlled by the two Byte Write Select
(BW
) and a Write Enable (WE) input. All writes are
[A:B]
conducted with on-chip synchronous self-timed write circuitry.
Three synchronous Chip Enables (CE
asynchronous Output Enable (OE) provide for easy bank
selection and output tri-state control. In order to avoid bus
contention, the output drivers are synchronously tri-stated
during the data portion of a write sequence.
A1'
Q1
A0'
Q0
S
E
N
S
MEMORY
E
WRITE
ARRAY
DRIVERS
A
M
P
S
INPUT
E
REGISTER 1
,
•
San Jose
CA 95134-1709
CY7C1352G
[1]
, CE
, CE
) and an
1
2
3
O
O
U
U
T
T
P
P
D
U
U
A
T
T
T
A
R
B
DQs
E
U
S
G
F
DQP
T
A
I
F
E
S
DQP
E
B
E
T
R
R
E
S
I
R
N
S
G
E
E
INPUT
E
REGISTER 0
•
408-943-2600
Revised July 4, 2006
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