Cypress Semiconductor NoBL CY7C1352G 사양 시트 - 페이지 3
{카테고리_이름} Cypress Semiconductor NoBL CY7C1352G에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor NoBL CY7C1352G 13 페이지. 4-mbit (256k x 18) pipelined sram with nobl architecture
페이지 인쇄Pin Definitions
Name
I/O
A0, A1, A
Input-
Synchronous
BW
Input-
[A:B]
Synchronous
WE
Input-
Synchronous
ADV/LD
Input-
Synchronous
CLK
Input-Clock
CE
Input-
1
Synchronous
CE
Input-
2
Synchronous
CE
Input-
3
Synchronous
OE
Input-
Asynchronous
CEN
Input-
Synchronous
ZZ
Input-
Asynchronous
DQs
I/O-
Synchronous
DQP
I/O-
[A:B]
Synchronous
MODE
Input Strap Pin Mode Input. Selects the burst order of the device.
V
Power Supply
DD
V
I/O Power Supply Power supply for the I/O circuitry.
DDQ
V
Ground
SS
NC
–
NC/36M,
–
NC/72M,
NC/144M,
NC/288M
Document #: 38-05514 Rev. *D
Address Inputs used to select one of the 256K address locations. Sampled at the rising
edge of the CLK. A
are fed to the two-bit burst counter.
[1:0]
Byte Write Inputs, active LOW. Qualified with WE to conduct writes to the SRAM. Sampled
on the rising edge of CLK.
Write Enable Input, active LOW. Sampled on the rising edge of CLK if CEN is active LOW.
This signal must be asserted LOW to initiate a write sequence.
Advance/Load Input. Used to advance the on-chip address counter or load a new address.
When HIGH (and CEN is asserted LOW) the internal burst counter is advanced. When LOW,
a new address can be loaded into the device for an access. After being deselected, ADV/LD
should be driven LOW in order to load a new address.
Clock Input. Used to capture all synchronous inputs to the device. CLK is qualified with CEN.
CLK is only recognized if CEN is active LOW.
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE
to select/deselect the device.
2
3
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE
to select/deselect the device.
1
3
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in conjunction
with CE
and CE
to select/deselect the device.
1
2
Output Enable, asynchronous input, active LOW. Combined with the synchronous logic
block inside the device to control the direction of the I/O pins. When LOW, the DQ pins are
allowed to behave as outputs. When deasserted HIGH, DQ pins are tri-stated, and act as input
data pins. OE is masked during the data portion of a write sequence, during the first clock when
emerging from a deselected state, when the device has been deselected.
Clock Enable Input, active LOW. When asserted LOW the Clock signal is recognized by the
SRAM. When deasserted HIGH the Clock signal is masked. Since deasserting CEN does not
deselect the device, CEN can be used to extend the previous cycle when required.
ZZ "sleep" Input. This active HIGH input places the device in a non-time-critical "sleep"
condition with data integrity preserved. During normal operation, this pin has to be low or left
floating. ZZ pin has an internal pull-down.
Bidirectional Data I/O Lines. As inputs, they feed into an on-chip data register that is triggered
by the rising edge of CLK. As outputs, they deliver the data contained in the memory location
specified by the address during the clock rise of the read cycle. The direction of the pins is
controlled by OE and the internal control logic. When OE is asserted LOW, the pins can behave
as outputs. When HIGH, DQ
s
automatically tri-stated during the data portion of a write sequence, during the first clock when
emerging from a deselected state, and when the device is deselected, regardless of the state
of OE.
Bidirectional Data Parity I/O Lines. Functionally, these signals are identical to DQ
write sequences, DQP
is controlled by BW
[A:B]
When tied to Gnd selects linear burst sequence. When tied to V
interleaved burst sequence.
Power supply inputs to the core of the device.
Ground for the device.
No Connects. Not internally connected to the die.
No Connects. Not internally connected to the die. NC/36M, NC/72M, NC/144M, NC/288M are
address expansion pins are not internally connected to the die.
Description
and DQP
are placed in a tri-state condition. The outputs are
[A:B]
correspondingly.
[A:B]
CY7C1352G
. During
s
or left floating selects
DD
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