Cypress Semiconductor NoBL CY7C1352G 사양 시트 - 페이지 8

{카테고리_이름} Cypress Semiconductor NoBL CY7C1352G에 대한 사양 시트을 온라인으로 검색하거나 PDF를 다운로드하세요. Cypress Semiconductor NoBL CY7C1352G 13 페이지. 4-mbit (256k x 18) pipelined sram with nobl architecture

페이지 인쇄

Switching Characteristics

Parameter
t
V
(typical) to the first Access
POWER
DD
Clock
t
Clock Cycle Time
CYC
t
Clock HIGH
CH
t
Clock LOW
CL
Output Times
t
Data Output Valid After CLK Rise
CO
t
Data Output Hold After CLK Rise
DOH
t
Clock to Low-Z
CLZ
t
Clock to High-Z
CHZ
t
OE LOW to Output Valid
OEV
t
OE LOW to Output Low-Z
OELZ
t
OE HIGH to Output High-Z
OEHZ
Set-up Times
t
Address Set-up Before CLK Rise
AS
t
ADV/LD Set-up Before CLK Rise
ALS
t
GW, BW
WES
[A:B]
t
CEN Set-up Before CLK Rise
CENS
t
Data Input Set-up Before CLK Rise
DS
t
Chip Enable Set-up Before CLK Rise
CES
Hold Times
t
Address Hold After CLK Rise
AH
t
ADV/LD Hold after CLK Rise
ALH
t
GW, BW
WEH
[A:B]
t
CEN Hold After CLK Rise
CENH
t
Data Input Hold After CLK Rise
DH
t
Chip Enable Hold After CLK Rise
CEH
Notes:
12. This part has a voltage regulator internally; tpower is the time that the power needs to be supplied above V
can be initiated.
13. t
, t
,t
, and t
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
CHZ
CLZ
OELZ
OEHZ
14. At any given voltage and temperature, t
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve tri-state prior to Low-Z under the same system conditions.
15. This parameter is sampled and not 100% tested.
16. Timing reference level is 1.5V when V
17. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
Document #: 38-05514 Rev. *D
Over the Operating Range
Description
[12]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
[13, 14, 15]
Set-Up Before CLK Rise
Hold After CLK Rise
is less than t
and t
is less than t
OEHZ
OELZ
CHZ
= 3.3V and is 1.25V when V
DDQ
DDQ
[16, 17]
–250
–200
Min.
Max.
Min.
Max.
1
1
4.0
5.0
1.7
2.0
1.7
2.0
2.6
2.8
1.0
1.0
0
0
2.6
2.8
2.6
2.8
0
0
2.6
2.8
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
0.3
0.5
minimum initially before a read or write operation
DD
to eliminate bus contention between SRAMs when sharing the same
CLZ
= 2.5V.
CY7C1352G
–166
–133
Min.
Max.
Min. Max.
1
1
6.0
7.5
2.5
3.0
2.5
3.0
3.5
4.0
1.5
1.5
0
0
3.5
4.0
3.5
4.0
0
0
3.5
4.0
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
Page 8 of 12
Unit
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
[+] Feedback