Avnet AES-LPA-502-G User Manual - Page 5
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2 Pin Assignment
The following sections provide information on assignment of signals to pins.
2.1
Digital IO & Power Rails
The Xilinx RFMC connector standard provides various digital IO and power rails. The AES-LPA-
502-G provides access to these signals at standard 0.1 mil headers J9, J10 and J29.
The tables below show how the GPIO pins have been assigned.
Differential Breakout card for Zynq UltraScale+ RFSoC – Hardware User's Guide
Figure 2 - Header Pins for RFMC Digital IO Signals
Figure 3 - Header Pins for RFMC I2C and Power Rails
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Hardware User's Guide