DG FPGA Setup

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DG FPGA Setup
dg_toeudp25gip_fpgasetup_xilinx.doc
FPGA setup for TOE/UDP25G-IP with CPU Demo
Rev2.0 7-Jun-21
1 Overview
This document describes how to setup FPGA board and prepare the test environment for running
TOE25G-IP/UDP25G-IP demo. The user can setup two test environments for transferring
TCP/UDP data via 25Gb Ethernet connection by using TOE25G-IP/UDP25G-IP, as shown in
Figure 1-1.
Figure 1-1 Two test environments for running the demo
7-Jun-21
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