HP StorageWorks 1000 - Modular Smart Array Resumo da tecnologia - Página 7

Procurar online ou descarregar pdf Resumo da tecnologia para Interruptor HP StorageWorks 1000 - Modular Smart Array. HP StorageWorks 1000 - Modular Smart Array 15 páginas. Power supply, computer
Também para HP StorageWorks 1000 - Modular Smart Array: Manual da rede (8 páginas), Lista de apoio (34 páginas), Manual de prevenção de erros (12 páginas), Livro Branco Técnico (12 páginas), Atualização do firmware (9 páginas), Visão geral (20 páginas), Manual de instalação (2 páginas), Números de telefone de apoio (19 páginas), Manual de referência (48 páginas), Manual de Administração (40 páginas), Nota de lançamento (13 páginas), Instruções de início rápido (8 páginas), Manual de início rápido (7 páginas), Nota de lançamento (5 páginas), Instruções de substituição (4 páginas), Livro Branco (13 páginas), Especificação rápida (17 páginas), Especificação (49 páginas), Manual de iniciação (34 páginas), Instalação (4 páginas), Manual de instalação (18 páginas), Manual de instruções de desmontagem (9 páginas), Manual de programação (8 páginas)

Multi-core technologies

In the past, the most common way to improve processor performance was to increase core

frequency and/or cache size. However, both of these solutions increase power consumption (and

heat generation) and have other limitations. Alternatively, higher performance can be achieved by

using multiple execution cores per processor. Multi-core processors run applications more efficiently

and allow multi-threaded software to achieve higher performance, while maintaining a similar

power budget to single-core processors. Also, multi-core processors are increasingly attractive with

reductions in the manufacturing process (for example, from 90 nm to 65 nm to 45 nm). This is

because smaller cores require less power, which permits more cores to be built into a single

processor.

AMD introduced its first dual-core AMD64 processor in 2005; it was manufactured using a 90 nm

process. The AMD Opteron processor is essentially divided into two parts: execution and

communications, with a system request interface and crossbar switch linking these two parts (see

Figure 2). The crossbar switch architecture enabled AMD Opteron processors to transition easily

from single-core to dual-core processors without fundamental design changes.

Each execution core includes a 64-KB/64-KB data/instruction L1 cache and a 1-MB L2 cache. The

system request interface manages and prioritizes the processor requests to the crossbar switch. The

crossbar switch connects both processor cores directly to communications: I/O (through

HyperTransport links) and the integrated memory controller. The memory controller and the

HyperTransport links remain the same as in a single core system.

Figure 2. The Socket F (1207) and Socket AM2 designs support dual-core AMD Revision F processors.

The primary difference between the processors designed for single, dual, or multi-core systems is in

the way the processor uses the HyperTransport link(s). In the 1000 series AMD Opteron processors,

the single HyperTransport link can only connect to I/O in a non-coherent link. This means that the

1000 series processors are limited to single-processor systems. In the 2000 series, one of three

HyperTransport links can connect to one other AMD Opteron processor in a coherent link. The