HP StorageWorks 1000 - Modular Smart Array 기술 개요 - 페이지 7

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HP StorageWorks 1000 - Modular Smart Array에 대해서도 마찬가지입니다: 네트워크 매뉴얼 (8 페이지), 지원 목록 (34 페이지), 오류 방지 매뉴얼 (12 페이지), 기술 백서 (12 페이지), 펌웨어 업데이트 (9 페이지), 개요 (20 페이지), 설치 매뉴얼 (2 페이지), 지원 전화번호 (19 페이지), 참조 매뉴얼 (48 페이지), 관리 매뉴얼 (40 페이지), 릴리스 노트 (13 페이지), 빠른 시작 지침 (8 페이지), 빠른 시작 매뉴얼 (7 페이지), 릴리스 노트 (5 페이지), 교체 지침 (4 페이지), 백서 (13 페이지), 빠른 사양 (17 페이지), 사양 (49 페이지), 시작하기 매뉴얼 (34 페이지), 설치 (4 페이지), 설치 매뉴얼 (18 페이지), 분해 지침 매뉴얼 (9 페이지), 프로그래밍 매뉴얼 (8 페이지)

Multi-core technologies

In the past, the most common way to improve processor performance was to increase core

frequency and/or cache size. However, both of these solutions increase power consumption (and

heat generation) and have other limitations. Alternatively, higher performance can be achieved by

using multiple execution cores per processor. Multi-core processors run applications more efficiently

and allow multi-threaded software to achieve higher performance, while maintaining a similar

power budget to single-core processors. Also, multi-core processors are increasingly attractive with

reductions in the manufacturing process (for example, from 90 nm to 65 nm to 45 nm). This is

because smaller cores require less power, which permits more cores to be built into a single

processor.

AMD introduced its first dual-core AMD64 processor in 2005; it was manufactured using a 90 nm

process. The AMD Opteron processor is essentially divided into two parts: execution and

communications, with a system request interface and crossbar switch linking these two parts (see

Figure 2). The crossbar switch architecture enabled AMD Opteron processors to transition easily

from single-core to dual-core processors without fundamental design changes.

Each execution core includes a 64-KB/64-KB data/instruction L1 cache and a 1-MB L2 cache. The

system request interface manages and prioritizes the processor requests to the crossbar switch. The

crossbar switch connects both processor cores directly to communications: I/O (through

HyperTransport links) and the integrated memory controller. The memory controller and the

HyperTransport links remain the same as in a single core system.

Figure 2. The Socket F (1207) and Socket AM2 designs support dual-core AMD Revision F processors.

The primary difference between the processors designed for single, dual, or multi-core systems is in

the way the processor uses the HyperTransport link(s). In the 1000 series AMD Opteron processors,

the single HyperTransport link can only connect to I/O in a non-coherent link. This means that the

1000 series processors are limited to single-processor systems. In the 2000 series, one of three

HyperTransport links can connect to one other AMD Opteron processor in a coherent link. The