HP 226824-001 - ProLiant - ML750 Giriş Kılavuzu - Sayfa 6

Masaüstü HP 226824-001 - ProLiant - ML750 için çevrimiçi göz atın veya pdf Giriş Kılavuzu indirin. HP 226824-001 - ProLiant - ML750 22 sayfaları. Visualization and acceleration in hp proliant servers
Ayrıca HP 226824-001 - ProLiant - ML750 için: Sıkça Sorulan Sorular (4 sayfalar), Uygulama Kılavuzu (35 sayfalar), Teknik Beyaz Kitap (12 sayfalar), Ürün Yazılımı Güncellemesi (9 sayfalar), Genel Bakış (20 sayfalar), Uygulama Kılavuzu (26 sayfalar), Sorun Giderme Kılavuzu (18 sayfalar), Uygulama Kılavuzu (11 sayfalar), Kurulum Kılavuzu (2 sayfalar), Yapılandırma Kılavuzu (2 sayfalar), Giriş Kılavuzu (19 sayfalar), Güncelleme Kılavuzu (9 sayfalar), Güncelleme Kılavuzu (16 sayfalar), Giriş Kılavuzu (12 sayfalar), Giriş Kılavuzu (10 sayfalar), Teknoloji Özeti (9 sayfalar)

Figure 3. By decreasing the amount of work done in each stage, the clock frequency can be increased.

A basic structure for a computer pipeline consists of the following four steps, which are performed

repeatedly to execute a program.

Fetch the next instruction from the address stored in the program counter.

Store that instruction in the instruction register, decode it, and increment the address in the

program counter.

Execute the instruction currently in the instruction register.

Write the results of that instruction from the execution unit back into the destination register.

Typical processor architectures split the pipeline into segments that perform those basic steps: the

"front end" of the microprocessor; the execution engine; and the retire unit (Figure 4). The front end

fetches the instruction and decodes it into smaller instructions (commonly referred to as micro-ops).

These decoded instructions are sent to one of the three types of execution units (integer, load/store, or

floating point) to be executed. Finally, the instruction is retired and the result is written back to its

destination register.

Figure 4. Basic 4-stage pipeline schematic