HP 226824-001 - ProLiant - ML750 Manuale introduttivo - Pagina 6

Sfoglia online o scarica il pdf Manuale introduttivo per Desktop HP 226824-001 - ProLiant - ML750. HP 226824-001 - ProLiant - ML750 22. Visualization and acceleration in hp proliant servers
Anche per HP 226824-001 - ProLiant - ML750: Domande frequenti (4 pagine), Manuale di implementazione (35 pagine), Libro bianco tecnico (12 pagine), Aggiornamento del firmware (9 pagine), Panoramica (20 pagine), Manuale di implementazione (26 pagine), Manuale di risoluzione dei problemi (18 pagine), Manuale di implementazione (11 pagine), Manuale di installazione (2 pagine), Manuale di configurazione (2 pagine), Manuale introduttivo (19 pagine), Manuale di aggiornamento (9 pagine), Manuale di aggiornamento (16 pagine), Manuale introduttivo (12 pagine), Manuale introduttivo (10 pagine), Brief tecnologico (9 pagine)

Stampa la pagina
HP 226824-001 - ProLiant - ML750 Manuale introduttivo
Figure 3. By decreasing the amount of work done in each stage, the clock frequency can be increased.
A basic structure for a computer pipeline consists of the following four steps, which are performed
repeatedly to execute a program.
Fetch the next instruction from the address stored in the program counter.
1.
Store that instruction in the instruction register, decode it, and increment the address in the
2.
program counter.
Execute the instruction currently in the instruction register.
3.
Write the results of that instruction from the execution unit back into the destination register.
4.
Typical processor architectures split the pipeline into segments that perform those basic steps: the
"front end" of the microprocessor; the execution engine; and the retire unit (Figure 4). The front end
fetches the instruction and decodes it into smaller instructions (commonly referred to as micro-ops).
These decoded instructions are sent to one of the three types of execution units (integer, load/store, or
floating point) to be executed. Finally, the instruction is retired and the result is written back to its
destination register.
Figure 4. Basic 4-stage pipeline schematic
6